1. Field of the Invention
The present invention relates to an analog-to-digital converter, especially an asynchronous successive approximation register analog-to-digital converter.
2. Description of the Prior Art
The asynchronous successive approximation register analog-to-digital converter (ASAR ADC) is a converter for converting continuous analog data into discrete binary digital signals. Because ASAR ADCs have advantages of low cost and high compatibility, ASAR ADCs are widely applied in the field of very large scale integration (VLSI) and system on chip (SOC), such as battery-powered instruments and quantizers. In general, an ASAR ADC includes a comparator for comparing a sample and hold clock with a reference voltage, to successively determine the digital code of each bit, until finishing the conversion of the least significant bit (LSB).
However, for an N-bit ASAR ADC, it is difficult to perform N-bit conversion because the meta-stability effect will occur when a prior art ASAR ADC performs multiple bit data processing, causing the total data comparison time being longer than the allowable time of the external clock. In other words, the low frequency of the external clocks makes the ASAR ADC unable to complete data comparison on time, thus the prior ASAR ADC is unable to correctly convert analog data into digital signals.